1. Field of the Invention
The present invention relates to binary differential demodulators. More specifically, the invention relates to non-redundant multi-error correcting differential demodulators for binary digital frequency or digital phase modulated signals.
2. Description of Related Art
Differential demodulators have been widely used in varieties of communication systems that use either digital frequency or digital phase modulated signals. Among those systems are IFF communication systems, underwater communication systems, mobile communication systems, satellite communication systems, etc. Differential demodulators require simpler circuits and they do not require carrier recovery. However, their bit error rate BER performance is inferior to that for the corresponding coherent demodulators. Coherent demodulators usually require carrier recovery and hence more complex circuits.
Non-redundant error correcting (NEC) techniques have been deployed to improve bit error rate performance of differential demodulators, similarly to conventional error correcting codes, but without the requirement for extra redundant bits, and extra bandwidth or power. See, e.g., U.S. Pat. Nos. 3,529,290 and 4,128,828. NEC techniques use outputs of several order (bits) differential detectors along with the outputs of a first order (conventional) differential detector in detecting and correcting erroneous data bits. Outputs of the first order detector have been used to recover modulated data and outputs of higher order detectors have been used as a parity check for the recovered data. NEC techniques offer varieties of error correcting capabilities, such as single-error correcting capability, double-error correcting capability, and triple-error correcting capability. As the order of error-correcting capability increases, the order of deployed differential detectors, and hence the demodulator complexity increase.
Techniques for single-error correcting capability have been proposed by T. Masamura, et al., “Differential Detection of MSK with Nonredundant Error Correction,” IEEE Trans. Communications, COM-27, June 1979; by S. Samejima et al., “Differential PSK System with Non-Redundant Error Correction,” IEEE Journal on Selected Areas in Comm., pp. 74-81, 1983; and by I. S. Barbounakis et al., “Duoquaternary FSK Receivers in Mobile Communications,” IEEE, VTC01, pp. 1987-1991, 2001. Techniques for double-error correcting capability have been proposed by T. Masamura, “Intersymbol Interference Reduction for Differential MSK by Nonredundant Error Correction,” IEEE Trans. On Vehicular Technology, Vol. 39, No. 1, pp. 27-36, February 1990, by Y. Ha et al., “DMSK System with Nonredundant Error Correction Capability,” IEEE GLOBECOM '91, pp. 770-774, 1991; and by I. S. Barbounakis et al., “Tamed Frequency Modulation Detection Analysis With NEC Receivers,” IEE Proc. Comm., Vol. 147, No. 4, pp. 149-154, 2000. Techniques for triple error correcting capability have been proposed by J. Yang, et al., “An Improved π/4—QPSK With Nonredundant Error Correction for Satellite Mobile Broadcasting,” IEEE Trans. On Broadcasting, Vol. 37, No. 1, pp. 9-16, 1991; and by D. P. C. Wong et al., “Nonredundant Error Correction Analysis and Evaluation of Differentially Detected π/4—shift DQPSK Systems in a Combined CCI and AWGN Environment,” IEEE Trans. on Vehicular Technology, Vol. 41, No. 1, pp. 35-48, 1992.
In the open literature cited above, both non-redundant error correcting (NEC) binary, and multi-level (M-ary) differential demodulators have been designed. The designed NEC binary differential demodulators, which are addressed by the present invention, have only either a single-error or a double-error correcting capability. These demodulators have been used with modulation structures such as differential minimum shift keying (DMSK), binary phase shift keying (BPSK), and tamed frequency modulation (TFM).
The common features of existing NEC binary demodulators are depicted in the table of FIG. 1. Among those features are the number of differential detectors required to correct k (k=1,2,3) consecutive errors, the erroneous bit to be corrected at an instant i, and the number of bits left without correction at the end of any correction cycle.
Each of the existing NEC binary and multi-level demodulators cited above encompasses four modules: (i) a differential detectors module, (ii) a syndrome generator module, (ii) a syndrome register module, and (iii) a pattern detector module. The algorithms used in building and operating those modules are as follows. For a demodulator with k (k=1,2,3) consecutive error correcting capability, the differential detectors module encompasses (k+1) differential detectors, and it delivers the outputs of those detectors to the syndrome generator. The syndrome generator compares the outputs of the first order detector against the outputs of each higher order differential detector, leading to a set of k syndromes. The generated set of syndromes is delivered to the syndrome register, where it is combined with other k delayed syndrome sets associated with previous time intervals, thereby forming a syndrome matrix having k×(k+1) dimensions. The syndrome matrices are delivered to the pattern detector, where they are compared against specified stored error patterns to detect, and hence correct, any error that may be found.
The algorithms used in existing NEC binary demodulators impose requirements that limit the performance of those demodulators. Such requirements discouraged the design of future demodulators with higher order error correcting capabilities, e.g. triple-error correcting capability, quadruple-error correcting capability, etc. The following equations illustrate how such requirements discourage the design of future NEC demodulators. First, note equation (1) that gives the number of syndromes, ns, required for the operation of a k (k=1,2,3) order error correcting capability:ns=k(k+1)  (1)
This number of syndromes gives a number of error patterns, nep, that should be searched for specified stored error patterns:nep=2k(k+1)  (2)
The number of stored error patterns, nsp, is given by:
                    nsp        =                              ∑                          i              =              0                                      k              -              1                                ⁢                      (                                                                                (                                          k                      +                      1                                        )                                    2                                -                1                            i                        )                                              (        3        )            
Each of the above stored patterns has a length of syndromes, ns. So multiplying equation (3) by equation (1) gives the memory required for storing the error patterns, memo, in bits, where:
                    memo        =                              k            ⁡                          (                              k                +                1                            )                                ⁡                      [                                          ∑                                  i                  =                  0                                                  k                  -                  1                                            ⁢                              (                                                                                                    (                                                  k                          +                          1                                                )                                            2                                        -                    1                                    i                                )                                      ]                                              (        4        )            
Equations (1)-(4) are used in the table of FIG. 2 and in FIG. 3 to obtain the requirements of existing single-error, and double-error correcting binary demodulators. Equations (1)-(4) are also used in FIGS. 2 and 3 to project the requirements for the design of similar future NEC binary demodulators with higher order-error correcting capabilities, e.g. triple-error, quadruple-error, and quintuple-error correcting demodulators.
From FIGS. 2 and 3, it is clear that number of searched error patterns, and the number of stored error patterns, increase exponentially as the order of error-correcting capabilities increases. This makes pattern detection processes deployed within existing demodulators more time consuming, more memory demanding, and less accurate. These drawbacks have discouraged further design of NEC binary demodulators having higher order error correcting capabilities.
From FIGS. 2 and 3 it is also clear that the limitations of existing NEC binary demodulators reside within the syndrome register modules and the pattern detector modules used by those demodulators. The syndrome registers impose the following limitations:
a) The memory required to store the syndrome matrices increases quadratically with the increase of error correcting capabilities (eq. 1); and
b) The use of delayed syndrome values by the syndrome registers makes the demodulators more vulnerable to error propagation.
As for pattern detectors, they impose the following limitations:
a) Pattern detectors require memories to store specified error patterns. Both the number of stored error patterns, and the length of required memory increase exponentially as the order of error correcting capabilities increases; and
b) Pattern detector processes performed within any pattern detector consume time and they may be associated with uncertainties, especially at higher-order correcting capabilities.
What is needed is a demodulator having higher order error-correcting capabilities that does not suffer the foregoing limitations.